40G QSFP+ to QSFP+ Active Optical Cable (AOC)

SPECIFICATIONS
Cable End Connector A	SFP+	Cable End Connector B	SFP+
Jumper Type	Direct-Attach	Data Rate	10G
Aggregate Bit Rate	10.3125Gbps	Lane Bit Rate	10Gbps
Number of Channels	1	Single Channel Rate	10G
Array Transmitter	VSCEL	Array Receiver	PIN
Minimum Bend Radius	30mm	Factory Brand	PHILISUN
Center(Operating) Wavelength	850nm	Bit Error Rate	≤10-12
Fiber Type	OM3 MMF MAX 300m	Cable Colour	Aqua
Cable Material	LSZH/OFNP	Cable Length Selection	1-300 meter
Safety Certification	TUV/UL/FDA	Application Scenarios	10 Gigabit Ethernet (10GbE)
Protocols	SFF-8636/SFF-8431/SFP MSA 10 Gigabit Ethernet 1x InfiniBand QDR, DDR, SDR	DDMI(Commercial)	YES
Supply Voltage	3.3V	Power Dissipation	<0.8W
Operating Temperature	0 to 70℃ (32 to 158℉)	Storage Temperature	-40 to 85℃ (-40to185℉)

PRODUCT PRESENTATION

The PHILISUN QSFP+(40G) Active Optical Cable is a direct-attach fiber assembly utilizing QSFP+ connectors and the Multi-Mode Fiber (MMF) scheme. The product complies with the SFF-8436 MSA standard and is suitable for 40Gbps connections within racks and across adjacent racks. It uses OM3 Multimode Fiber. Its compact structure and fully sealed integrated optics reduce costs compared to conventional optical modules and jumpers, while significantly improving reliability and reducing maintenance. This AOC guarantees broad compatibility with major vendor platforms including Cisco, H3C, Huawei, Juniper, and Arista, and more.

AOC SERIES PRODUCTS

PRODUCTION & TESTING EQUIPMENT

PERFORMANCE PARAMETER

Absolute Maximum Ratings
Parameter	Symbol	Min	Typ.	Max	Unit	Notes
Operating Case Temperature	TC	0	–	70	。C	–
Ambient Humidity	HA	5	–	85	%	1
Storage Ambient Humidity	HA	0	–	85	%	–
+3.3V Supply Voltage	V CC3	3.135	3.3	3.465	V	–
+3.3V Supply Current	IVCC3	–	–	400	mA	–
Total Power Dissipation	PD	–	–	1.4	W	–
Fiber Bend Radius	Rb	3	–	–	cm	–
Bit rate	B	1	–	10.5	Gb/s	2
Module Turn-on Time	–	–	–	2000	ms	3
Input Control Voltage- High	ViH	2	–	Vcc+0.3	V	4
Input Control Voltage – Low	ViL	-0.3	–	0.8	V	4
Digital Output Voltage- High	VoH	2	–	Vcc+0.3	–	5
Digital Output Voltage- Low	VoL	0	–	0.8	–	5
Clock Rate-I2C	–	–	–	400	kHz	6
Notes: 1. Non-condensing 2.Tested with PRBS 231-1, BER 1X10-12 3.Time from module power-on / insertion/ ResetL deassert to module full functional. 4. For all control input pins: LPMode, Reset and ModSelL 5. For all status output pins: ModPrsL, IntL 6. For management interface.

QSFP+ AOC Specifications
Parameter	Value	Unit	Notes
Module Form Factor	QSFP+	–	Supports SFF8431/SFF8432/SFF8472
Number of Lanes	4 Tx and 4 Rx	–	–
Maximum Aggregate Data Rate	41.2	Gb/s	–
Maximum Data Rate per Lane	10.3	Gb/s	No retimer or CDR devices embedded in the module. Allows operation at data-rates below 10.3 Gbps
Protocols Supported	Typical applications include Fibre Channel, 40G Ethernet, SATA/SAS3	–	–
Bit Error Rate Performance	<10E-12	–	–
Management Interface	Serial, I2C-based, 400 kHz maximum frequency	–	As defined by the QSFP+ MSA
Power Consumption per end	540	mW	Nominal Power
Electrical Interface and Pin-out	38-pin edge connector	–	Pin-out as defined by the QSFP+ MSA

Optical Characteristics
Parameter	Symbol	Min	Typ.	Max	Unit	Notes
Transmitter
Center Wavelength	λc	840	850	860	nm	–
RMS spectral width	Δλ	–	–	0.65	nm	–
Average launch power, each lane	Pout	-7.5	–	2.5	dBm	–
Difference in launch power between any two lanes (OMA)	–	–	–	4	dB	–
Extinction Ratio	ER	3	–	–	dB	–
Peak power, each lane	–	–	–	4	dBm	–
Transmigrate and dispersion penalty (TDP), each lane	TDP	–	–	3.5	dB	–
Average launch power of OFF transmitter, each lane	–	–	–	-30	dB	–
Eye Mask coordinates: X1, X2, X3, Y1, Y2, Y3	SPECIFICATION VALUES 0.23, 0.34, 0.43, 0.27, 0.35, 0.4					Hit Ratio = 5×10-5
Receiver
Center Wavelength	λc	840	850	860	nm	–
Stressed receiver sensitivity in OMA, each lane	–	–	–	-5.4	dBm	1
Maximum Average power at receiver input, each lane	–	–	–	2.4	dBm	–
Receiver Reflectance	–	–	–	-12	dB	–
Peak power, each lane	–	–	–	4	dBm	–
LOS Assert	–	-30	–	–	dBm	–
LOS De-Assert – OMA	–	–	–	-7.5	dBm	–
LOS Hysteresis	–	0.5	–	–	dB	–
Note: 1. Measured with conformance test signal at TP3 for BER = 10e-12

QSFP+ MODULE PAD LAYOUT

PIN DESCRIPTION

Pin	Logic	Symbol	Name/Description	Notes
1	–	GND	Ground	1
2	CML-I	Tx2n	Transmitter Inverted Data Input	–
3	CML-I	Tx2p	Transmitter Non-inverted Data Input	–
4	–	GND	Ground	1
5	CML-I	Tx4n	Transmitter Inverted Data Input	–
6	CML-I	Tx4p	Transmitter Non-inverted Data Input	–
7	–	GND	Ground	1
8	LVTTL-I	ModSelL	Module Select	–
9	LVTTL-I	ResetL	Module Reset	–
10	–	Vcc Rx	+3.3V Power Supply Receiver	–
11	LVCMOS-I/O	SCL	2-Wire Serial Interface Clock	2
12	LVCMOS-I/O	SDA	2-Wire Serial Interface Data	2
13	–	GND	Ground	1
14	CML-O	Rx3p	Receiver Non-Inverted Data Output	–
15	CML-O	Rx3n	Receiver Inverted Data Output	–
16	–	GND	Ground	1
17	CML-O	Rx1p	Receiver Non-Inverted Data Output	–
18	CML-O	Rx1n	Receiver Inverted Data Output	–
19	–	GND	Ground	1
20	–	GND	Ground	1
21	CML-O	Rx2n	Receiver Inverted Data Output	–
22	CML-O	Rx2p	Receiver Non-Inverted Data Output	–
21	CML-O	Rx2n	Receiver Inverted Data Output	–
22	CML-O	Rx2p	Receiver Non-Inverted Data Output	–
23	–	GND	Ground	1
24	CML-O	Rx4n	Receiver Inverted Data Output	–
25	CML-O	Rx4p	Receiver Non-Inverted Data Output	–
26	–	GND	Ground	1
27	LVTTL-O	ModPrsL	Module Present	2
28	LVTTL-O	IntL	Interrupt	2
29	–	Vcc Tx	+3.3V Power Supply Transmitter	–
30	–	Vcc1	+3.3V Power Supply	–
31	LVTTL-I	LPMode	Low Power Mode	–
32	–	GND	Ground	1
33	CML-I	Tx3p	Transmitter Non-inverted Data Input	–
34	CML-I	Tx3n	Transmitter Inverted Data Input	–
35	–	GND	Ground	1
36	CML-I	Tx1p	Transmitter Non-inverted Data Input	–
37	CML-I	Tx1n	Transmitter Inverted Data Input	–
38	–	GND	Ground	1
Notes: 1. Module ground pins GND are isolated from the module case and chassis ground within the module. 2. Shall be pulled up with 4.7K-10Kohms to a voltage between 3.14V and 3.47V on the host board.

PRODUCT CERTIFICATION

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CONFIGURATION INFORMATION

40G QSFP+ to QSFP+ Active Optical Cable (AOC)

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