400G QSFP-DD to QSFP-DD Active Optical Cable (AOC)

Compliant with theSFF-8436 QSFP-DD MSA standard
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SPECIFICATIONS
Cable End Connector ASFP+Cable End Connector BSFP+
Jumper TypeDirect-AttachData Rate10G
Aggregate Bit Rate10.3125GbpsLane Bit Rate10Gbps
Number of Channels1Single Channel Rate10G
Array TransmitterVSCELArray ReceiverPIN
Minimum Bend Radius30mmFactory BrandPHILISUN
Center(Operating) Wavelength850nmBit Error Rate≤10-12
Fiber TypeOM3 MMF MAX 300mCable ColourAqua
Cable MaterialLSZH/OFNPCable Length Selection1-300 meter
Safety CertificationTUV/UL/FDAApplication Scenarios10 Gigabit Ethernet (10GbE)
ProtocolsSFF-8636/SFF-8431/SFP MSA
10 Gigabit Ethernet
1x InfiniBand QDR, DDR, SDR
DDMI(Commercial)YES
Supply Voltage3.3VPower Dissipation<0.8W
Operating Temperature0 to 70℃ (32 to 158℉)Storage Temperature-40 to 85℃ (-40to185℉)

 

PRODUCT PRESENTATION
The PHILISUN QSFP-DD(200G) Active Optical Cable is a direct-attach fiber assembly utilizing QSFP-DD connectors and the Multi-Mode Fiber (MMF) scheme. The product complies with the SFF-8665 MSA standard and is suitable for 200Gbps connections within racks and across adjacent racks. It uses OM3/OM4 Multimode Fiber. Its compact structure and fully sealed integrated optics reduce costs compared to conventional optical modules and jumpers, while significantly improving reliability and reducing maintenance. This AOC guarantees broad compatibility with major vendor platforms including Cisco, H3C, Huawei, Juniper, and Arista, and more.

 

AOC SERIES PRODUCTS

 

PRODUCTION & TESTING EQUIPMENT

 

PERFORMANCE PARAMETER
Absolute Maximum Ratings
Parameter Symbol Unit Min Max.
Storage Temperature Range Ts -40 +85
Relative Humidity RH % 0 85
Power Supply Voltage VCC V -0.3 +3.465

 

Recommended Operating Conditions
Parameter Symbol Unit Min Typ. Max.
Operating Case Temperature Range Tc 0 70
Power Supply Voltage VCC V 3.135 3.3 3.465
Bit Rate(Per channel) BR GBd 26.5625

 

Electric Ports Definition
Parameter Symbol Unit Min. Typ. Max. Note
Supply Voltage VCC
VCC3.3-Tx
VCC3.3-Rx
V 3.135 3.3 3.465
Power Consumption Pc W 8.5
Transceiver MgmtInitDuration Time ms 2000
Transmitter
Differential Peak-to-Peak Input Voltage tol mV 900 10%
Differential Termination Mismatch V
Differential Input Return Loss(SDD11) dB IEEE
Equation
(83E-5)
Common-Mode to Differential
Conversion and Differential to
Common-Mode
Conversion(SCD11,SDC11)
dB IEEE
Equation
(83E-6)
Stressed Input Test IEEE
120E.3.4.1
Vcsel Wavelength nm 840 850 860
Vcsel Beam Divergence 25。
Receiver
Differential Peak-to-Peak Output Voltage mV 900
DC Common Mode Voltage Vcm mV -350 2850
Common Mode Noise, RMS VcmAC mV 17.5
Differential Termination Mismatch % 10
Differential Output Return
Loss(SDD22)
dB IEEE
Equation
(83E-2)
Common-mode to Differential
Conversion and Differential to
Common-Mode
Conversion(SCD22,SDC22)
dB IEEE
Equation
(83E-3)
Near-End ESMW (Eye Symmetry Mask Width) UI 0.265
Near-End Eye Height, Differential mV 70
Far-End ESMW (Eye Symmetry Mask Width) UI 0.2
Far-End Eye Height, Differential mV 30
PD Wavelength nm 840 850 860
IIC communication
IIC Clock Frequency kHZ / 400 1000
Clock Stretching us / / 500

 

PIN DESCRIPTIONS

Electrical Pin-out Details

 

PIN Logic Symbol Description Note
1 GND Ground 1
2 CML-I Tx2n Transmitter Inverted Data Input
3 CML-I Tx2p Transmitter Non-Inverted Data output
4 GND Ground 1
5 CML-I Tx4n Transmitter Inverted Data Input
6 CML-I Tx4p Transmitter Non-Inverted Data output
7 GND Ground 1
8 LVTTL-I ModSelL Module Select
9 LVTTL-I ResetL Module Reset
10 VccRx +3.3V Power Supply Receiver 2
11 LVCOMS-I/O SCL 2-Wire Serial Interface Clock
12 LVCOMS-I/O SDA 2-Wire Serial Interface Data
13 GND Ground 1
14 CML-0 Rx3p Receiver Non-Inverted Data Output
15 CML-0 Rx3n Receiver Inverted Data Output
16 GND Ground 1
17 CML-0 Rx 1p Receiver Non-Inverted Data Output
18 CML-0 Rx 1n Receiver Inverted Data Output
19 GND Ground 1
20 GND Ground 1
21 CML-0 Rx2n Receiver Inverted Data Output
22 CML-0 Rx2p Receiver Non-Inverted Data Output
23 GND Ground 1
24 CML-0 Rx4n Receiver Inverted Data Output
25 CML-0 Rx4p Receiver Non-Inverted Data Output
26 GND Ground 1
27 LVTTL-0 ModPrsL Module Present
28 LVTTL-0 IntL Interrupt
29 VccTx +3.3 V Power Supply transmitter 2
30 Vcc1 +3.3 V Power Supply 2
31 LVTTL-I LPMode Low Power mode
32 GND Ground 1
33 CML-I Tx3p Transmitter Inverted Data Input
34 CML-I Tx3n Transmitter Non-Inverted Data output
35 GND Ground 1
36 CML-I Tx 1p Transmitter Inverted Data Input
37 CML-I Tx 1n Transmitter Non-Inverted Data output
38 GND Ground 1
39 GND Ground 1
40 CML-I Tx6n Transmitter Inverted Data Input
41 CML-I Tx6p Transmitter Non-Inverted Data output
42 GND Ground 1
43 CML-I Tx8n Transmitter Inverted Data Input
44 CML-I Tx8p Transmitter Non-Inverted Data output
45 GND Ground 1
46 Reserved For future use 3
47 VS1 Module Vendor Specific 1 3
48 VccRx1 +3.3V Power Supply Receiver 2
49 VS2 Module Vendor Specific 2 3
50 VS3 Module Vendor Specific 3 3
51 GND Ground 1
52 CML-0 Rx7p Receiver Non-Inverted Data Output
53 CML-0 Rx7n Receiver Inverted Data Output
54 GND Ground 1
55 CML-0 Rx5p Receiver Non-Inverted Data Output
56 CML-0 Rx5n Receiver Inverted Data Output
57 GND Ground 1
58 GND Ground 1
59 CML-0 Rx6n Receiver Inverted Data Output
60 CML-0 Rx6p Receiver Non-Inverted Data Output
61 GND Ground 1
62 CML-0 Rx8n Receiver Inverted Data Output
63 CML-0 Rx8p Receiver Non-Inverted Data Output
64 GND Ground 1
65 NC Not Connect 3
66 Reserved For future use 3
67 VccTx 1 +3.3 V Power Supply transmitter 2
68 Vcc2 +3.3 V Power Supply 2
69 Reserved For future use 3
70 GND Ground 1
71 CML-I Tx7p Transmitter Inverted Data Input
72 CML-I Tx7n Transmitter Non-Inverted Data output
73 GND Ground 1
74 CML-I Tx5p Transmitter Inverted Data Input
75 CML-I Tx5n Transmitter Non-Inverted Data output
76 GND Ground 1
Notes:
1. QSFP-DD uses common ground (GND) for all signals and supply (power). All the common within the  QSFP-DD module and all module voltages are referenced to this potential unless otherwise noted. Connected theses directly to the host board signal common ground plane.2. VccRx, VccRx 1, Vcc1, Vcc2, VccTx, and VccTx 1 shall be applied concurrently. Requirements defined for  the host side of the Host Card Edge Connector are listed in Table 4. VccRx, VccRx 1, Vcc1, Vcc2, VccTx, and VccTx 1 may be internally connected within the module in any combination. The connector Vcc pins are each rated for a maximum current of 1000mA.

3. All Vendor Specific, Reserved and No Connect pins may be terminated with 50 ohms to ground on the host. Pad 65 (No Connect) shall be left unconnected within the module. Vendor Specific and Reserved pads shall    have an impedance than 10 kOhms and less than 100pF.

 

PRODUCT CERTIFICATION

 

COMPATIBLE BRANDS
CONFIGURATION INFORMATION
光模块产品详情订购信息---SFP28