400G QSFP-DD to 8×50G SFP56 Active Optical Cable(AOC)

Compliant with QSFP-DD MSA/SFP28 MSA和IEEE 802.3cd standard
Switch to Switch
Switch to GPU

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SPECIFICATIONS
Cable End Connector AQSFP-DDCable End Connector B8×SFP56
Jumper TypeActive Optical Breakout CableData Rate400G
Aggregate Bit Rate425GbpsLane Bit Rate53.125Gbps
Number of Channels8Single Channel Rate50G
Array TransmitterVSCELArray ReceiverPIN
Minimum Bend Radius30mmFactory BrandPHILISUN
Center(Operating) Wavelength850nmBit Error Rate2.4E-4
Fiber TypeOM3 MMF MAX 70m/OM4 MMF MAX 100mCable ColourAqua
Cable MaterialLSZH/OFNPCable Length Selection1-100meter
Safety CertificationTUV/UL/FDAApplication Scenarios400 Gigabit Ethernet (400GbE)
ProtocolsQSFP-DD MSA/SFP6 MSA/IEEE 802.3cdDDMI(Commercial)YES
Supply Voltage3.3VPower DissipationQSFP-DD:<10.0W
QSFP56:<3.0W
Operating Temperature0 to 70℃ (32 to 158℉)Storage Temperature-20 to 85℃ (-4 to 185℉)

 

PRODUCT PRESENTATION
The PHILISUN 400G QSFP-DD to 8x50G SFP56 Active Optical Cable (AOC) provides the highest-density breakout solution, segmenting a single 400G QSFP-DD port into eight individual 50G SFP56 channels. It is fully compliant with QSFP-DD MSA, SFP28 MSA, and the IEEE 802.3cd standard, ensuring reliable performance across massive aggregation layers. This AOC is ideal for connecting high-density Switch to Switch matrices and maximizing bandwidth efficiency between Switch to GPU nodes in large-scale HPC and AI clusters.

 

AOC SERIES PRODUCTS

 

PRODUCTION & TESTING EQUIPMENT

 

PERFORMANCE PARAMETER
Absolute Maximum Ratings
Parameter Symbol Unit Min. Max.
Storage Temperature Range TC ℃ -40 +85
Relative Humidity RH % 0 85
Power Supply Voltage VCC V -0.5 +3.6

 

Recommended Operating Conditions
Parameter Symbol Unit Min. Typ. Max.
Operating Case Temperature Range Tca ℃ 0 – 70
Power Supply Voltage VCC V 3.15 3.3 3.45
Supply Current SFP56 end Icc mA – 26.5625 900
Data Rate Per Lane DR Gbps – 53.125 –
Fiber Bend Radius Rb cm 3 – –
Notes:
1. Supply current is shared between VCCTX and VCCRX.
2. In-rush is defined as current level above steady state current requirements.

 

Transmitter Specifications
Parameter Symbol Unit Min. Typ.      Max.
Input Differential Impedance Rin – 90 100 110
Differential Input Voltage swing, per lane Vin – 300 – 1100
Transmit Disable Voltage VD – 2.0 –      VCC+0.3
Transmit Enable Voltage Ven – Vee –      Vee+0.8

 

Receiver Specifications
Parameter Symbol Unit Min. Typ. Max.
Differential Output Swing, per lane Vout mV 300 – 900
Bit Error Rate@53.125 Gbps BER – – – 2.4E-4
Output Differential Impedance Rout Ω 90 100 110
Loss of Signal –Asserted – V 2.0 – VCC+0.3
Loss of Signal –Negated – V Vee – Vee+0.8

 

Transceiver Electrical Pad Layout（QSFP- DD end）

 

QSFP- DD to 8*SFP56  Pin Function Definition
Pin Symbol Name/Description Note
1 GND Ground 1
2 Tx2 n Transmitter  Inverted  Data  Input –
3 Tx2 p Transmitter  Non- Inverted  Data  Output –
4 GND Ground 1
5 Tx4 n Transmitter  Inverted  Data  Input –
6 Tx4p Transmitter  Non- Inverted  Data  Input –
7 GND Ground 1
8 ModSelL Module  Select –
9 ResetL Module  Reset –
10 VccRx + 3.3 V Power Supply Receiver 2
11 SCL 2 – wire serial interface clock –
12 SDA 2 – wire serial interface data –
13 GND Ground 1
14 Rx3p Receiver  Non- Inverted  Data Output –
15 Rx3n Receiver  Inverted  Data  Output –
16 GND Ground 1
17 Rx1p Receiver  Non- Inverted  Data Output –
18 Rx1n Receiver  Inverted  Data  Output –
19 GND Ground 1
20 GND Ground 1
21 Rx2n Receiver  Inverted  Data  Output –
22 Rx2p Receiver  Non- Inverted  Data Output –
23 GND Ground 1
24 Rx4n Receiver  Inverted  Data  Output –
25 Rx4p Receiver  Non- Inverted  Data Output –
26 GND Ground 1
27 Mod PrsL Module  Present –
28 IntL Interrupt –
29 VccTx + 3.3 V Power supply transmitter 2
30 Vcc1 + 3.3V Power supply 2
31 InitMode Initialization mode;  In legacy QSFP applications,  the
InitMode pad is called LPMODE		 –
32 GND Ground 1
33 Tx3p Transmitter  Non- Inverted  Data  Input –
34 Tx3 n Transmitter  Inverted  Data  Input –
35 GND Ground 1
36 Tx1 p Transmitter  Non- Inverted  Data  Input –
37 Tx1 n Transmitter  Inverted  Data  Input –
38 GND Ground 1
39 GND Ground 1
40 Tx6 n Transmitter  Inverted  Data  Input –
41 Tx6p Transmitter  Non- Inverted  Data  Input –
42 GND Ground 1
43 Tx8 n Transmitter  Inverted  Data  Input –
44 Tx8p Transmitter  Non- Inverted  Data  Input –
45 GND Ground 1
46 Reserved For future use 3
47 VS1 Module Vendor Specific  1 3
48 VccRx1 3.3 V Power Supply Receiver 2
49 VS2 Module Vendor Specific 2 3
50 VS3 Module Vendor Specific 3 3
51 GND Ground 1
52 Rx7p Receiver  Non- Inverted  Data Output –
53 Rx7n Receiver  Inverted  Data  Output –
54 GND Ground 1
55 Rx5p Receiver  Non- Inverted  Data Output –
56 Rx5n Receiver  Inverted  Data  Output –
57 GND Ground 1
58 GND Ground 1
59 Rx6n Receiver  Inverted  Data  Output –
60 Rx6p Receiver  Non- Inverted  Data Output –
61 GND Ground 1
62 Rx8n Receiver  Inverted  Data  Output –
63 Rx8p Receiver  Non- Inverted  Data Output –
64 GND Ground 1
65 NC No  Connect 3
66 Reseved For future use 3
67 VccTx1 3.3 V Power Supply 2
68 Vcc2 3.3 V Power Supply 2
69 Reseved For future use 3
70 GND Ground 1
71 Tx7p Transmitter  Non- Inverted  Data  Input –
72 Tx7 n Transmitter  Inverted  Data  Input –
73 GND Ground 1
74 Tx5p Transmitter  Non- Inverted  Data  Input –
75 Tx5 n Transmitter  Inverted  Data  Input –
76 GND Ground 1
Notes:
1. QSFP- DD TO 4  QSFP uses common ground ( GND) for all signals and supply ( power) .  All are common within the QSFP- DD TO 4 QSFP module and all  module voltages are  referenced to this  potential  unless otherwise  noted.  Connect these directly to the host board signal- common ground  plane.2. VccRx, VccRx1 , Vcc1 , Vcc2 , VccTx and VccTx1  shall be applied concurrently.  Requirements defined for the host side of the Host Card Edge Connector are listed in Table 6. VccRx, VccRx1 , Vcc1 , Vcc2 , VccTx and VccTx1  may be internally connected within the module in any combination.  The connector Vcc pins are each rated for a maximum current of 1000 mA.

3. All Vendor Specific,  Reserved and No Connect pins may be terminated with 5 0  ohms to ground on the host.  Pad 6 5  ( No Connect)shall be left unconnected within the module.  Vendor specific and Reserved pads shall have an impedance to GND that is greater than 10 kOhms and less than 100 pF.

4. Plug Sequence specifies the mating sequence of the host connector and module. The sequence is 1 A,  2 A,  3 A,  1 B,  2 B,  3 B. (see Figure 2 for pad locations)  Contact sequence A will make,  then break contact with additional QSFP- DD TO 2  QSFP pads.Sequence 1 A,  1B will then occur simultaneously, followed by 2 A,  2 B, followed by 3 A, 3 B.

 

Transceiver Electrical Pad Layout（SFP56 end）

 

Pin Definition（SFP56 end）
Pin Symbol Name/Description
1 VEET Transmitter Ground
2 Tx_FAULT Transmitter Fault
3 Tx_DIS Transmitter Disable. Laser out put disabled on high or open
4 SDA 2-wire Serial Inter face Data Line
5 SCL 2-wire Serial Inter face Clock Line
6 MOD_ABS Module Absent. Grounded with in the module
7 RS0 Rate Select 0
8 RX_LOS Loss of Signal in dication. Logic 0 indicates normal operation
9 RS1 Rate Select 1
10 VEER Receiver Ground
11 VEER Receiver Ground
12 RD- Receiver Inverted DATA out. AC Coupled
13 RD+ Receiver DATA out. AC Coupled
14 VEER Receiver Ground
15 VCCR Receiver Power Supply
16 VCCT Transmitter Power Supply
17 VEET Transmitter Ground
18 TD+ Transmitter DATA in. AC Coupled
19 TD- Transmitter Inverted DATA in. AC Coupled
20 VEET Transmitter Ground

 

PRODUCT CERTIFICATION

 

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